The present invention relates to liquid crystal display devices, and more particularly to a simplified method for fabricating liquid crystal displays in which an organic or inorganic insulating layer can be applied as a passivation layer according to the thickness of a semiconductor layer or etching selection ratio of the etch stopper layer.
An important display device, the cathode ray tube(CRT) display device has a large screen area. However, since the screen on which the luminescence material is coated must be separated from the electron gun a distance greater than that prescribed for the large screen area, a CRT display device has a large volume. Therefore, CRT devices cannot be used in a low power consumption portable television, small notebook computers or the like.
Among the various flat panel display devices characterized by low power consumption and small size, such as LCD(liquid crystal display), PDP(plasma display panel), VFD(vacuum florescent display), and ELD(electromagnetic display), the LCD has emerged because of its capability for high resolution.
FIG. 1 is a partial plan view of an AMLCD. This LCD is a TFT(thin film transistor) LCD. In this figure, a plurality of pixels are formed in a matrix shape by a plurality of gate bus lines 1 and data bus lines 7 which extend in the horizontal and vertical directions. For explanatory purposes, only one pixel is described. In the pixel, pixel electrode 9 is formed and TFT 2 is formed at the intersection of gate bus line 1 and data bus line 7. A gate electrode 11 and source/drain electrode 17 of TFT 2 are connected to gate bus line 1 and data bus line 7, respectively. When a voltage is applied to gate bus line 1 from the gate driver circuit(not shown) TFT 2 is turned on, and at the same time, the signal is applied to the pixel electrode 9 from a data driver circuit(not shown) through TFT 2.
There are two types of inverted stagger structure TFTs. One is ES TFT(etch stopper TFT) and the other is BCE TFT(back channel etched TFT). In the ES TFT, the ES layer is formed over the semiconductor layer to prevent the channel region of the semiconductor layer from being etched when the semiconductor layer and the source/drain electrodes are etched. In the BCE TFT, since there is no insulating layer on the semiconductor layer, the process is simpler, although the semiconductor layer in the channel region is etched during the process.
FIGS. 2a-2f illustrate various steps of the conventional process for fabricating a TFT with inverted stagger structure. As shown in FIG. 2a, metal is first deposited on to a transparent glass substrate 10 and etched to form a gate electrode 11. Over the substrate 10 and gate electrode 11, as shown in FIG. 2b, gate insulating layer 13, amorphous silicon(a-Si) layer 14a, and insulating layer 15a are successively deposited. The insulating layer 15a is etched to form and ES layer 15, as shown in FIG. 2c.
As shown in FIGS. 2d and 2e, n.sup.+ a-Si layer 16a and metal layer 17a are deposited after a-Si layer 14a is etched to form a semiconductor layer 14. To form ohmic contact layer 16 and the source/drain electrodes 17, the n.sup.+ a-Si layer 16 and metal layer 17a are etched. As a result, a portion of ES layer 15 overlaps n.sup.+ layer 16 and another portion is exposed. On source/drain electrodes 17 and ES layer 15, the passivation layer(not shown) is deposited. A contact hole is formed in the passivation layer and the pixel electrode 9 covers pixel region to connect it to source/drain electrodes 17.
In this process, since ES layer 15 covers the channel region of semiconductor layer 14, the channel region is non affected during the etching of the a-Si 14a and the n.sup.+ a-Si 16a layers. As shown in the figures, however, six masks are needed to fabricate the TFT of the LCD; that is, masks for forming the gate electrodes, ES layer, semiconductor layer, source/drain electrodes and n.sup.+ layer, contact hole, and pixel electrode. The resulting process is complex and costly.